// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module conv_24b_to_32b 
(
    input  wire          I_clk,
    input  wire          I_new_frame,
    input  wire [ 23: 0] I_data,
    input  wire          I_data_valid,
    output reg  [ 31: 0] O_data,
    output reg           O_data_valid
);

/******************************************************************************
                                <localparams>
******************************************************************************/

/******************************************************************************
                              <internal signals>
******************************************************************************/
reg  [ 23: 0] last_data;
reg  [ 1: 0] phase;

/******************************************************************************
                                <module body>
******************************************************************************/
always @(posedge I_clk)
    if (I_new_frame)
        phase <= 'd0;
    else if (I_data_valid)
        phase <= phase + 1'b1;

always @(posedge I_clk)
    if (I_data_valid)
        case (phase)
            0: O_data <= {8'd0,I_data[23:0]};
            1: O_data <= {I_data[7:0],O_data[23:0]};
            2: O_data <= {I_data[15:0],last_data[23:8]};
            3: O_data <= {I_data[23:0],last_data[23:16]};
        endcase

always @(posedge I_clk)
    if (I_data_valid)
        last_data <= I_data;

always @(posedge I_clk)
    if (I_new_frame)
        O_data_valid <= 1'b0;
    else
        O_data_valid <= I_data_valid && (phase != 'd0);

endmodule
`default_nettype wire

